The present invention relates to a digital computer and more particularly to a microprogrammable digital processor, memory, logic and control and addressing structure which may be implemented in TTL logic or as an LSI (large scale integration) chip. Moreover, this invention particularly relates to a processor apparatus and method for the microinstruction memory addressing of expanded memory space connected, externally, to the processor. The subject invention, furthermore, is designed for a particular type of microprogrammable units as embodied in the teachings of Faber in patent application U.S. Ser. No. 307,863, now U.S. Pat. No. 3,878,514, filed Nov. 20, 1972 and assigned to the assignee of the present application. The programmable unit disclosed therein is a self-contained serial-bit-by-byte processor employing a soft machine architecture through microprogramming. An instruction set, at the microprogram level, is provided for controlling the specific circuitry of the processor in executing basic computer operations. Essentially, the specific circuitry represents minimally committed logic or hardware which becomes committed to a specific task by control signals originating in the instruction set. Logic, control and addressing functions are performed by circuitry which includes only those gates, registers, drivers, and related logic, which are necessary to implement the basic operations.
Such a processing unit may be comprised of five functional parts: (1) a logic unit which performs shifting, arithmetic and logic functions; (2) a microprogram memory which stores both literals and control words; (3) a memory control unit which provides the registers mircoprogram memory addressing; (4) a control unit which provides timing and conditional control, successor determination and instruction decoding; and (5) an external interface.
In the microprocessor, cited above, a microprogram memory (MPM) is addressed by a memory program count register (MPCR). Feeding this (MPCR) register is an alternate memory program count register (AMPCR). The AMPCR receives instructions from the microprogram memory as well as from other registers within the processor.
Microprocessors of the Faber type are being used in larger and more complicated processing tasks than for which they were originally designed. While this processor's logic units and control units are sophisticated enough to handle the enlarged processing tasks, the micromemory capacity as designed into the basic apparatus is not large enough. This disadvantage exists in most microprocessors in the class of Faber-size processors. The compactness of the basic processor as implemented in a single MOS chip or in a single TTL-printed circuit card unit did not, with yesterday's technology, permit extensive micromemory capacity.
It is, therefore, desirable to be able to increase micromemory capacity. One approach is to connect external memory modules to the basic processor, accessing external memory locations from within the processor, and calling in instructions and data words from the external locations as needed. However, when the basic processor is one wherein component-resources, such as buffer capacities, and address register capacities, are already fully utilized, the implementation of increased micromemory capacity via externally coupled memories is not easily accomplished.
An objective of this invention therefore is to provide an apparatus for accessing external micromemory capacity from within a microprocessor.
Another objective of this invention is to provide an apparatus for accessing microinstruction memory locations external to a microprocessor without the alteration of the hardware design of the basic microprocessor.
A further objective of this invention is to provide simplified firmware for driving the external micromemory apparatus with the base processor, operating within pre-existing format specification.